Embodiments of the present embodiments relate to an electrostatic discharge (ESD) protection circuit having a primary discharge device and plural avalanche diodes. Preferred embodiments of the circuit are intended for use at input, output, input-output, or power supply terminals of an integrated circuit.
Referring to FIG. 1A, there is an ESD protection circuit of the prior art as disclosed by Yu in U.S. Pat. No. 6,472,286. The circuit of FIG. 1A is a cross section of a multi finger NPN bipolar transistor as described at col. 3, line 31 through col. 4, line 8. The circuit is fabricated on a P-type substrate 10 with a heavily doped N+ layer 12. An N-type layer 14 is formed over layer 12. A P-type base region 24 is formed at a surface of the substrate 10 and connected to P+ region 22. An N+ emitter region 26 is formed within base region 24. A deep N+ region 16 is connected to N+ layer 12 and serves as a collector surface contact. Surface contacts 18, 20, and 28 for respective collector, base, and emitter regions are formed over the surface of the substrate 10.
FIG. 1B discloses a typical current-voltage characteristic of a bipolar NPN transistor as illustrated at FIG. 1A (col. 1, lines 31-61). The wave form illustrates three points of interest for a bipolar NPN transistor characteristic. First is the initial collector-base breakdown voltage BVcbo, which may also be referred to as the collector-base avalanche threshold, first breakdown, or Vt1, It1. The second point is BVceo which may also be referred to as the snapback voltage. The third point is Vt2, It2, which is the transition point between NPN avalanche conduction and second breakdown.
There are several problems with the circuit of FIG. 1A and the associated current-voltage characteristic of FIG. 1B. First, BVcbo is approximately 18 V and may exceed the damage threshold (Vdam) of contemporary integrated circuits the ESD protection circuit is to protect. Second, BVceo is approximately 8 V and may be less than the operating voltage of the integrated circuit the ESD protection circuit is to protect, thereby causing electrical overstress (EOS) after an ESD event. Finally, the deep N+ collector contact region 16 of FIG. 1A must be spaced apart from P+ base contact region 22 to avoid avalanche conduction and to provide sufficient area for lateral diffusion in subsequent high temperature processing steps of the integrated circuit. Various embodiments of the present disclosure are directed to solving these and other problems and improving operation of the ESD protection circuit without increasing process complexity.